`default_nettype none
`timescale 1ns / 1ps

module main;

reg			clk;
reg [15:0]	din;
reg 		wr_en;
wire 		sclk;
wire 		sync;
wire		sdout;
	
DacDriver #(
	.CLK_DIV( 4 )
)
dut (
	.clk(clk),
	.din(din),
	.wr_en(wr_en),
	.sclk(sclk),
	.sync(sync),
	.sdout(sdout)
);

initial begin
    $dumpfile("dac_driver.vcd");
    $dumpvars;
    	clk = 0;
    	din = 27;
    	wr_en = 0;
    #10 wr_en = 1;
    #10 wr_en = 0;
	#20000 $stop;
end

always #5 clk = !clk;

endmodule


